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DOCUMENT NUMBER 9S12KT256DGV1/D
MC9S12K-Family Device User Guide V01.05
Original Release Date: 16 JUL 2002 Revised: 14 NOV 2003
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c)Motorola, Inc., 2003
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Device User Guide -- 9S12KT256DGV1/D V01.05
Revision History
Version Revision Number Date
01.00 01.01 01.02 01.03 01.04 16 JUL 02 22 NOV 02 15 JAN 03 13 JUN 03 18 JUN 03
Author
Original Version.
Description of Changes
Change load cap value on VDD and VDDPLL. Correct expanded bus timing from 20MHz to 25 MHz. Move ATD interrupt vector from $ffd0 to $ffd2. Change PWeh and tDSW parameter in external bus timing. Expand to a K-Family SoC Guide and include 9S12KT256. Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256. Changed to a Device User Guide and added Document number. Updated Table A-17 Oscillator Characteristics. Replaced XCLKS with PE7 for Clock Selection diagrams. Added CTRL to Table 2-1 Signal Properties. Replaced Burst programming with Row Programming in NVM electricals. Changed Digital logic to Internal Logic. Added LRAE bootloader information. Changed PWEL, PWEH, tDSW, tACCE, tNAD, tNAV, tRWV, tLSV, tNOV, tP0V and tP1V in the external bus timing. Added voltage regulator characteristics.
01.05
14 NOV 03
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Device User Guide -- 9S12KT256DGV1/D V01.05
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MC9S12KG128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MC9S12KT256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.4 VREGEN -- Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.5 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin . . . . . 58 2.3.7 PAD[15:8] / AN[15:8] -- Port AD Input Pins [15:8]. . . . . . . . . . . . . . . . . . . . . . . . 58 2.3.8 PAD[7:0] / AN[7:0] -- Port AD Input Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3.9 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 58 2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 58 2.3.11 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3.12 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.13 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.14 PE4 / ECLK -- Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.15 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.16 PE2 / R/W -- Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.17 PE1 / IRQ -- Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.18 PE0 / XIRQ -- Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.19 PH7 / KWH7 / SS2 -- Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.20 PH6 / KWH6 / SCK2 -- Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.21 PH5 / KWH5 / MOSI2 -- Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.22 PH4 / KWH4 / MISO2 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Device User Guide -- 9S12KT256DGV1/D V01.05
2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56
PH3 / KWH3 / SS1 -- Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PJ7 / KWJ7 / TXCAN4 / SCL -- PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . 62 PJ6 / KWJ6 / RXCAN4 / SDA -- PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . 62 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PK7 / ECS / ROMCTL -- Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 62 PM7 / TXCAN4 -- Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PM6 / RXCAN4 -- Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PM5 / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . 63 PM4 / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . 63 PM3 / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . 63 PM2 / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . 63 PM1 / TXCAN0 -- Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PM0 / RXCAN0 -- Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PP7 / KWP7 / PWM7 / SCK2 -- Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . 64 PP6 / KWP6 / PWM6 / SS2 -- Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PP5 / KWP5 / PWM5 / MOSI2 -- Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . 64 PP4 / KWP4 / PWM4 / MISO2 -- Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . 64 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 64 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . 64 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . 65 PS7 / SS0 -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS6 / SCK0 -- Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS5 / MOSI0 -- Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS4 / MISO0 -- Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.1 VDDX,VSSX -- Power Supply Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . 66
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Device User Guide -- 9S12KT256DGV1/D V01.05
2.4.2 66 2.4.3 2.4.4 2.4.5 2.4.6
VDDR, VSSR -- Power Supply Pins for I/O Drivers & for Internal Voltage Regulator VDD1, VDD2, VSS1, VSS2 -- Power Supply Pins for Internal Logic . . . . . . . . . 66 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 67 VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 67 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 67
Section 3 System Clock Description Section 4 Modes of Operation
4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Section 5 Resets and Interrupts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.1 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 6 HCS12 Core Block Description
6.1 6.2 6.3 6.4 6.5 6.6 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 HCS12 Background Debug Module (BDM) Block Description . . . . . . . . . . . . . . . . . 75 HCS12 Debug (DBG) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 76 HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . 76
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Device User Guide -- 9S12KT256DGV1/D V01.05
Section 7 Analog to Digital Converter (ATD) Block Description Section 8 Clock Reset Generator (CRG) Block Description
8.1 Consult the CRG Block Guide for information about the Clock and Reset Generator module.Device-specific information76
Section 9 EEPROM Block Description Section 10 Flash EEPROM Block Description Section 11 IIC Block Description Section 12 MSCAN Block Description Section 13 OSC Block Description Section 14 Port Integration Module (PIM) Block Description Section 15 Pulse Width Modulator (PWM) Block Description Section 16 Serial Communications Interface (SCI) Block Description Section 17 Serial Peripheral Interface (SPI) Block Description Section 18 Timer (TIM) Block Description Section 19 Voltage Regulator (VREG) Block Description
19.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 19.1.1 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 85 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A.2 Voltage Regulator (VREG_3V3) Operating Characteristics . . . . . . . . . . . . . . . . . . . 91 A.3 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 92 A.4 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 A.4.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 A.4.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 A.5 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 A.5.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 A.5.2 Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 A.5.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 A.6 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 A.6.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 A.6.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 A.7 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 A.7.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 A.7.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 A.7.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 A.8 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 A.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 A.9.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 A.9.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 A.10 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 A.10.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Appendix B Package Information
B.1 B.2 B.3 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 3-1 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure B-1 Figure B-2
MC9S12KG128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MC9S12KT256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MC9S12KG128 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . 23 MC9S12KT256 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . 24 Pin assignments 112 LQFP for MC9S12K-Family. . . . . . . . . . . . . . . . . . . . . 52 Pin assignments in 80 QFP for MC9S12K-Family. . . . . . . . . . . . . . . . . . . . . 53 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Loop Controlled Pierce Oscillator Connections (PE7=1). . . . . . . . . . . . . . . . 59 Full Swing Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . 59 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 92 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . 122 112-pin LQFP Mechanical Dimensions (case no. 987) . . . . . . . . . . . . . . . 123
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Table 0-1 Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 2-1 Table 2-2 Table 2-3 Table 4-1 Table 4-2 Table 4-3 Table 5-1 Table 5-2 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Table 19-1 Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table A-17 Table A-18 Table A-19
Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MC9S12KG128 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MC9S12KT256 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 41 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Clock selection based on PE7 during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 84 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Preliminary 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5V ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.3V ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5V ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.3V ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Startup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table A-20 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table A-21 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Table A-22 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table A-23 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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Preface
The Device User Guide provides information about the MC9S12K-Family devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes all the individual Block Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide. Table 0-1 Document References
User Guide
CPU12 Reference Manual HCS12 Background Debug (BDM) Block Guide HCS12 Debug (DBG) Block Guide HCS12 Interrupt (INT) Block Guide HCS12 Multiplexed Expanded Bus Interface (MEBI) Block Guide HCS12 Module Mapping Control (MMC) Block Guide Analog to Digital Converter: 10-Bit, 16 Channels (ATD_10B16C) Block Guide Analog to Digital Converter: 10-Bit, 8 Channels (ATD_10B8C) Block Guide Clock and Reset Generator (CRG) Block Guide 2K Byte EEPROM (EETS2K) Block Guide 4K Byte EEPROM (EETS4K) Block Guide 128K Byte Flash with Error Code Correction (FTS128K1ECC) Block Guide 256K Byte Flash with Error Code Correction (FTS256K2ECC) Block Guide Inter IC Bus (IIC) Block Guide Motorola Scalable CAN (MSCAN) Block Guide Oscillator Loop Control Pierce (OSC_LCP) Block Guide Port Integration Module(1) (PIM_9KG128) Block Guide Port Integration Module(2) (PIM_9KT256) Block Guide Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide Serial Communications Interface (SCI) Block Guide Serial Peripheral Interface (SPI) Block Guide Timer: 16-Bit, 8 Channels (TIM_16B8C) Block Guide Voltage Regulator (VREG_3V3) Block Guide NOTES: 1. Block Guide for MC9S12KG128 only. 2. Block Guide for MC9S12KT256 only.
Version
V02 V04 V01 V01 V03 V04 V03 V03 V04 V01 V02 V01 V01 V02 V02 V01 V01 V01 V01 V02 V03 V01 V01
Document Order Number
S12CPUV2/D S12BDMV4/D S12DBGV1/D S12INTV1/D S12MEBIV3/D S12MMCV4/D S12ATD10B16CV3/D1 S12ATD10B8CV3/D2 S12CRGV4/D S12EETS2KV1/D(1) S12EETS4KV2/D(2) FTS128K1ECCV1/D(1) FTS256K2ECCV1/D(2) S12IICV2/D S12MSCANV2/D S12OSCLCPV1/D S12KG128PIMV1/D S12KT256PIMV1/D S12PWM8B6CV1/D S12SCIV2/D S12SPIV3/D S12TIM16B8CV1/D S12VREG3V3V1/D
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Section 1 Introduction
1.1 Overview
The MC9S12K-Family is a 112/80 pin 16-bit Flash-based microcontroller family targeted for high reliability systems. Members of the MC9S12K-Family have an increased performance in reliability over the life of the product due to a built-in Error Checking and Correction Code (ECC) in the Flash memory. The program and erase operations automatically generate six parity bits per word making ECC transparent to the user. All members of the MC9S12K-Family are comprised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), 128K or 256K bytes of Flash EEPROM, 2K or 4K bytes of EEPROM, 8K or 12K bytes of RAM, two asynchronous serial communications interface (SCI), three serial peripheral interface (SPI), IIC-bus, an 8-channel IC/OC timer, 16-channel or two 8-channel 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), two or three CAN 2.0 A, B software compatible modules, 29 discrete digital I/O channels (Port A, Port B, Port E and Port K), and 20 discrete digital I/O lines with interrupt and wakeup capability. The MC9S12K-Family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.
1.2 Features
* HCS12 Core - 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing - - - - - * - - - MEBI (Multiplexed External Bus Interface) MMC (Memory Map and Interface) INT (Interrupt Controller) DBG (Debugger) BDM (Background Debug Mode) 4Mhz to 16Mhz frequency range Pierce with amplitude loop control Clock monitor
Oscillator
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*
Clock and Reset Generator (CRG) - - - - Phase-locked loop clock frequency multiplier Self Clock mode in absence of external clock COP watchdog Real Time interrupt (RTI) 128K or 256K Byte Flash EEPROM i. Internal program/erase voltage generation ii. Security and Block Protect bits iii. Hamming Error Correction Coding (ECC) - - 2K or 4K Byte EEPROM 8K or 12K Byte static RAM Single-cycle misaligned word accesses without wait states
*
Memory -
*
Analog-to-Digital Converter(s) (ADC) - - - One 16-channel module with 10-bit resolution for MC9S12KG128 Two 8-channel module with 10-bit resolution for MC9S12KT256 External conversion trigger capability Programmable input capture or output compare channels Simple PWM mode Counter Modulo Reset External Event Counting Gated Time Accumulation Programmable period and duty cycle per channel 8-bit 8-channel or 16-bit 4-channel Edge and center aligned PWM signals Emergency shutdown input Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up
*
8-channel Timer (TIM) - - - - -
*
8-channel Pulse Width Modulator (PWM) - - - -
*
Two or Three 1M bit per second, CAN 2.0 A, B software compatible modules - - -
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- - * - - - * - - - * - - - * * - - -
Low-pass filter wake-up function Loop-back for self test operation Two asynchronous serial communication interface (SCI) Three synchronous serial peripheral interface (SPI) Inter-IC Bus (IIC) Input voltage range from 3.15V to 5.5V Low power mode capability Low Voltage Reset (LVR) and Low Voltage Interrupt (LVI) Rising or falling edge triggered interrupt capability Digital filter to prevent short pulses from triggering interrupts Programmable pull ups and pull downs 50MHz equivalent to 25MHz Bus Speed I/O lines with 3.3V/5V input and drive capability 3.3V/5V A/D converter inputs
Serial interfaces
Internal 2.5V Regulator
20 key wake up inputs
Operating frequency for ambient temperatures (TA -40C to 125C) 112-Pin LQFP or 80-Pin QFP package
1.3 Modes of Operation
* Normal modes - - - - - * - - - Normal Single-Chip Mode Normal Expanded Wide Mode1 Normal Expanded Narrow Mode1 Emulation Expanded Wide Mode1 Emulation Expanded Narrow Mode1 Special Single-Chip Mode with active Background Debug Mode Special Test Mode1 (Motorola use only) Special Peripheral Mode1 (Motorola use only)
Special Operating Modes
NOTES: 1. Expanded modes are only available in the 112 pin package version.
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*
Each of the above modes of operation can be configured for three Low power submodes - - - Stop Mode Pseudo Stop Mode Wait Mode
*
Secure operation, preventing the unauthorized read and write of the memory contents.
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1.4 MC9S12KG128 Block Diagram
128K Byte Flash EEPROM 2K Byte EEPROM 8K Byte RAM
AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD MISO MOSI SCK SS VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
ATD
PAD
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XTAL EXTAL VSSPLL VDDPLL XFC RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST
Voltage Regulator
DDRK
PPAGE
Single-wire BDM
OSC PLL
Periodic Interrupt COP Watchdog Clock Monitor CRG XIRQ IRQ R/W LSTRB ECLK MODA MODB NOACC/XCLKS
CPU12
PTK
PAD
ECS
DDRT
Breakpoints Debugger
TIM
DDRE
DDRS
SPI0 Multiplexed Address/Data Bus CAN0 DDRA PTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DDRM
DDRB PTB CAN4
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 RxCAN TxCAN
Module to Port Routing
RxCAN TxCAN
PTS
SCI1
PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7
Multiplexed Wide Bus
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
IIC
SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS
KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
Multiplexed Narrow Bus
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DDRP
Internal Logic 2.5V
VDD1,2 VSS1,2
I/O Driver 3.3V/5V
VDDX VSSX
OSC/PLL 2.5V
VDDPLL
VSSPLL
DDRH
VSSR
VDDA VSSA
SPI2
Figure 1-1 MC9S12KG128 Block Diagram
PTH
Voltage Regulator 3.3V/5V A/D Converter 3.3V/5V VDDR Voltage Reference
SPI1
PTP
PWM
Signals shown in Bold are not available on n the 80 Pin Package
System Integration Module (SIM)
PTE
PTT PTJ PTM
SCI0
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
DDRJ
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1.5 MC9S12KT256 Block Diagram
256K Byte Flash EEPROM 4K Byte EEPROM 12K Byte RAM
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
ATD0
ATD1
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XTAL EXTAL VSSPLL VDDPLL XFC RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST
Voltage Regulator
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD
AD0
DDRK
PPAGE
Single-wire BDM
OSC PLL
Periodic Interrupt COP Watchdog Clock Monitor CRG XIRQ IRQ R/W LSTRB ECLK MODA MODB NOACC/XCLKS
CPU12
PTK
AD1
ECS
DDRT
Breakpoints Debugger
TIM
DDRE
DDRS
SPI0 Multiplexed Address/Data Bus CAN0
MISO MOSI SCK SS
DDRM
DDRA PTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
RxCAN TxCAN RxCAN CAN1 TxCAN RxCAN CAN4 TxCAN
PTS
SCI1
PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7
Multiplexed Wide Bus
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
IIC
SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS
KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
Multiplexed Narrow Bus
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DDRP
Internal Logic 2.5V
VDD1,2 VSS1,2
I/O Driver 3.3V/5V
VDDX VSSX
OSC/PLL 2.5V
VDDPLL
VSSPLL
DDRH
VSSR
VDDA VSSA
SPI2
Figure 1-2 MC9S12KT256 Block Diagram
20
PTH
Voltage Regulator 3.3V/5V A/D Converter 3.3V/5V VDDR Voltage Reference
SPI1
PTP
PWM
Signals shown in Bold are not available on n the 80 Pin Package
System Integration Module (SIM)
PTE
PTT PTJ PTM
SCI0
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Module to Port Routing
DDRJ
Device User Guide -- 9S12KT256DGV1/D V01.05
1.6 Device Memory Map
Table 1-1 shows the device register map of the MC9S12KG128 after reset. Table 1-2 shows the device register map of the MC9S12KT256 after reset. Figure 1-3 and Figure 1-4 illustrate the full device memory map of the MC9S12KG128 and MC9S12KT256 respectively. Table 1-1 MC9S12KG128 Device Memory Map
Address
$000 - $017 $018 $019 $01A - $01B $01C - $01F $020 - $02F $030 - $033 $034 - $03F $040 - $06F $070 - $07F $080 - $0AF $0B0 - $0C7 $0C8 - $0CF $0D0 - $0D7 $0D8 - $0DF $0E0 - $0E7 $0E8 - $0EF $0F0 - $0F7 $0F8 - $0FF $100- $10F $110- $11B $11C - $13F $140 - $17F $180 - $23F $240 - $27F $280 - $2BF $2C0 - $2E7 $2E8 - $3FF Reserved Voltage Regulator (VREG) Device ID register (PARTID) CORE (MEMSIZ, IRQ, HPRIO) CORE (DBG) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Standard Timer 16-bit 8 channels (TIM) Reserved Analog to Digital Converter 10-bit 16 channels (ATD) Reserved Serial Communications Interface 0 (SCI0) Serial Communications Interface 1 (SCI1) Serial Peripheral Interface 0 (SPI0) Inter Integrated Circuit Bus (IIC) Reserved Serial Peripheral Interface 1 (SPI1) Serial Peripheral Interface 2 (SPI2) Flash Control Register EEPROM Control Register Reserved Motorola Scalable Controller Area Network 0 (CAN0) Reserved Port Integration Module (PIM) Motorola Scalable Controller Area Network 4 (CAN4) Pulse Width Modulator 8-bit 8 channels (PWM) Reserved
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Size
24 1 1 2 4 16 4 12 48 16 48 24 8 8 8 8 8 8 8 16 12 36 64 192 64 64 40 280
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Device User Guide -- 9S12KT256DGV1/D V01.05
Table 1-2 MC9S12KT256 Device Memory Map
Address
$000 - $017 $018 $019 $01A - $01B $01C - $01F $020 - $02F $030 - $033 $034 - $03F $040 - $06F $070 - $07F $080 - $09F $0A0 - $0C7 $0C8 - $0CF $0D0 - $0D7 $0D8 - $0DF $0E0 - $0E7 $0E8 - $0EF $0F0 - $0F7 $0F8 - $0FF $100- $10F $110- $11B $11C - $11F $120 - $13F $140 - $17F $180 - $1BF $1C0 - $23F $240 - $27F $280 - $2BF $2C0 - $2E7 $2E8 - $3FF Reserved Voltage Regulator (VREG) Device ID register (PARTID) CORE (MEMSIZ, IRQ, HPRIO) CORE (DBG) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Standard Timer 16-bit 8 channels (TIM) Reserved Analog to Digital Converter 10-bit 8 channels (ATD0) Reserved Serial Communications Interface 0 (SCI0) Serial Communications Interface 1 (SCI1) Serial Peripheral Interface 0 (SPI0) Inter Integrated Circuit Bus (IIC) Reserved Serial Peripheral Interface 1 (SPI1) Serial Peripheral Interface 2 (SPI2) Flash Control Register EEPROM Control Register Reserved Analog to Digital Converter 10-bit 8 channels (ATD1) Motorola Scalable Controller Area Network 0 (CAN0) Motorola Scalable Controller Area Network 1 (CAN1) Reserved Port Integration Module (PIM) Motorola Scalable Controller Area Network 4 (CAN4) Pulse Width Modulator 8-bit 8 channels (PWM) Reserved
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Size
24 1 1 2 4 16 4 12 48 16 32 40 8 8 8 8 8 8 8 16 12 4 32 64 64 128 64 64 40 280
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0000 $0000 $0400 $0800 $1000 $2000 $03FF $0800 $0FFF $2000 $4000 $3FFF $4000
1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM Mappable to any 2K Boundary 8K Bytes RAM Mappable to any 8K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window eight * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM (1K RAM hidden behind Register Space) $0000 - $07FF: 2K EEPROM (not visible)
Figure 1-3 MC9S12KG128 User Configurable Memory Map
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0000 $0000 $0400 $1000 $03FF $0000 $0FFF $1000 $4000 $3FFF $4000
1K Register Space Mappable to any 2K Boundary 4K Bytes EEPROM Mappable to any 4K Boundary 12K Bytes RAM Mappable to any 16K Boundary and alignable to top or bottom 0.5K, 1K, 2K or 4K Protected Sector
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window sixteen * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $1000 - $3FFF: 12K RAM $0000 - $0FFF: 4K EEPROM (1K hidden behind Register Space)
Figure 1-4 MC9S12KT256 User Configurable Memory Map
1.7 Detailed Register Map
()()The following tables() show the detailed register map of the MC9S12K-Family. $0000 - $000F
Address $0000 $0001 Name PORTA PORTB Read: Write: Read: Write:
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Bit 7 Bit 7 Bit 6 6 6 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 Bit 2 2 2 Bit 1 1 1 Bit 0 Bit 0 Bit 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0000 - $000F
$0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: 6 6 0 0 0 0 6 6 0 MODB 0 0 0 0 5 5 0 0 0 0 5 5 PIPOE MODA 0 0 0 0 4 4 0 0 0 0 4 4 NECLK 0 PUPEE RDPE 0 0 3 3 0 0 0 0 3 3 LSTRE IVIS 0 0 0 0 2 2 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 1 1 0 0 0 0 Bit 1 0 0 EMK PUPBE RDPB 0 0 Bit 0 Bit 0 0 0 0 0 Bit 0 0 0 EME PUPAE RDPA ESTR 0
$0010 - $0014
Address $0010 $0011 $0012 $0013 $0014 Name INITRM INITRG INITEE MISC Reserved
MMC map 1 of 4 (HCS12 Module Mapping Control)
Bit 7 Read: RAM15 Write: Read: 0 Write: Read: EE15 Write: Read: 0 Write: Read: 0 Write: Bit 6 RAM14 REG14 EE14 0 0 Bit 5 RAM13 REG13 EE13 0 0 Bit 4 RAM12 REG12 EE12 0 0 Bit 3 RAM11 REG11 EE11 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 RAMHAL 0 EEON
EXSTR1 EXSTR0 ROMHM ROMON 0 0 0 0
$0015 - $0016
Address $0015 $0016 Name ITCR ITEST Read: Write: Read: Write:
INT map 1 of 2 (HCS12 Interrupt)
Bit 7 0 INTE Bit 6 0 INTC Bit 5 0 INTA Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0017 - $0017
Address $0017 Name Reserved Read: Write:
MMC map 2 of 4 (HCS12 Module Mapping Control)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0018 - $0018
Address $0018 Name Reserved Read: Write:
Miscellaneous Peripherals (Device Guide)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0019 - $0019
Address $0019 Name VREGCTRL Read: Write:
VREG3V3 (Voltage Regulator)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 LVDS Bit 1 LVIE Bit 0 LVIF
$001A - $001B
Address $001A $001B Name PARTIDH PARTIDL Read: Write: Read: Write:
Miscellaneous Peripherals (Device Guide)
Bit 7 ID15 ID7 Bit 6 ID14 ID6 Bit 5 ID13 ID5 Bit 4 ID12 ID4 Bit 3 ID11 ID3 Bit 2 ID10 ID2 Bit 1 ID9 ID1 Bit 0 ID8 ID0
$001C - $001D Guide)
Address $001C $001D Name MEMSIZ0 MEMSIZ1
MMC map 3 of 4 (HCS12 Module Mapping Control, Device
Bit 7 Bit 6 Bit 5 Bit 4 Read: reg_sw0 0 eep_sw1 eep_sw0 Write: Read: rom_sw1 rom_sw0 0 0 Write: Bit 3 0 0 Bit 2 Bit 1 Bit 0 ram_sw2 ram_sw1 ram_sw0 0 pag_sw1 pag_sw0
$001E - $001E
Address $001E Name INTCR Read: Write:
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 IRQE Bit 6 IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$001F - $001F
Address $001F Name HPRIO Read: Write:
INT map 2 of 2 (HCS12 Interrupt)
Bit 7 PSEL7 Bit 6 PSEL6 Bit 5 PSEL5 Bit 4 PSEL4 Bit 3 PSEL3 Bit 2 PSEL2 Bit 1 PSEL1 Bit 0 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0020 - $002F
Addres s $0020 $0021 $0022
$0023 $0024 $0025 $0026 $0027
DBG (including BKP) map 1of 1 (HCS12 Debug)
Bit 7 read DBGEN write AF read write read Bit 15 write
read write read write read write read write read write Bit 7 TBF PAGSEL Bit 15 Bit 7 14 6 13 5 12 4
Name DBGC1
-
Bit 6
ARM BF Bit 14 Bit 6 0
Bit 5
TRGSEL CF Bit 13 Bit 5
Bit 4
BEGIN 0 Bit 12 Bit 4
Bit 3
DBGBRK
Bit 2
0 TRG
Bit 1
Bit 0
CAPMOD
DBGSC
DBGTBH DBGTBL DBGCNT DBGCCX DBGCCH DBGCCL -
Bit 11 Bit 3 CNT
Bit 10 Bit 2
Bit 9 Bit 1
Bit 8 Bit 0
EXTCMP 11 3 10 2 9 1 RWCEN RWBEN Bit 8 Bit 0 RWC RWB
$0028 $0029 $002A
$002B $002C $002D $002E $002F
DBGC2
BKPCT0
DBGC3
BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
read BKABEN FULL BDM TAGAB BKCEN TAGC write read BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA write read PAGSEL EXTCMP write
read write read write read write read write read write Bit 15 Bit 7 PAGSEL Bit 15 Bit 7 14 6 13 5 12 4 14 6 13 5 12 4 11 3 EXTCMP 11 3 10 2 10 2
9 1
Bit 8 Bit 0
9 1
Bit 8 Bit 0
$0030 - $0031
Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write:
MMC map 4 of 4 (HCS12 Module Mapping Control)
Bit 7 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0032 - $0033
Address $0032 $0033 Name PORTK DDRK Read: Write: Read: Write:
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7 Bit 7 Bit 7 Bit 6 6 6 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 Bit 2 2 2 Bit 1 1 1 Bit 0 Bit 0 Bit 0
$0034 - $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP
CRG (Clock and Reset Generator)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 Write: Read: 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 Write: Read: TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 Write: Read: 0 LOCK TRACK SCM RTIF PROF LOCKIF SCMIF Write: Read: 0 0 0 0 0 RTIE LOCKIE SCMIE Write: Read: PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI Write: Read: 0 CME PLLON AUTO ACQ PRE PCE SCME Write: Read: 0 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 Write: Read: 0 0 0 WCOP RSBCK CR2 CR1 CR0 Write: Read: 0 0 0 0 RTIBYP COPBYP PLLBYP FCM Write: Read: TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0 Write: Read: 0 0 0 0 0 0 0 0 Write: Bit 7 6 5 4 3 2 1 Bit 0
$0040 - $006F
Address $0040 $0041 $0042 $0043 $0044 $0045 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo)
TIM (Timer 16 Bit 8 Channels)
Bit 7 Read: IOS7 Write: Read: 0 Write: FOC7 Read: OC7M7 Write: Read: OC7D7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0040 - $006F
Address $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 $0059 $005A $005B $005C $005D $005E Name TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi)
TIM (Timer 16 Bit 8 Channels)
Bit 7 Read: TEN Write: Read: TOV7 Write: Read: OM7 Write: Read: OM3 Write: Read: EDG7B Write: Read: EDG3B Write: Read: C7I Write: Read: TOI Write: Read: C7F Write: Read: TOF Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Bit 6 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 Bit 5 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 C5F 0 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 Bit 4 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 C4F 0 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 Bit 3 0 TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 Bit 2 0 TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 Bit 1 0 TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 Bit 0 0 TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0040 - $006F
Address $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 $006A $006B $006C $006D $006E $006F Name TC7 (lo) PACTL PAFLG PACNT (hi) PACNT (lo) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
TIM (Timer 16 Bit 8 Channels)
Bit 7 Bit 7 0 0 Bit 7 Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 6 PAEN 0 6 6 0 0 0 0 0 0 0 0 0 0 0 0 Bit 5 5 PAMOD 0 5 5 0 0 0 0 0 0 0 0 0 0 0 0 Bit 4 4 PEDGE 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 Bit 3 3 CLK1 0 3 3 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 2 CLK0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 Bit 1 1 PAOVI PAOVF 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 Bit 0 PAI PAIF Bit 0 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0
$0070 - $007F
Address $0070 - $007F Name Reserved Read: Write:
Reserved space
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0080 - $00AF
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 Name ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0 Reserved ATDTEST0 ATDTEST1 ATDSTAT0 ATDSTAT1 ATDDIEN1 ATDDIEN0 PORTAD1 PORTAD0 ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H
ATD (Analog to Digital Converter 10 Bit 16 Channel)1
Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF15 Write: Read: CCF7 Write: Read: IEN15 Write: Read: IEN7 Write: Read: PTAD15 Write: Read: PTAD7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 CCF14 CCF6 IEN14 IEN6 PTAD14 PTAD6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 CCF13 CCF5 IEN13 IEN5 PTAD13 PTAD5 13 0 13 0 13 0 13 0 13 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 0 0 CCF10 CCF2 IEN10 IEN2 PTAD10 PTAD2 10 0 10 0 10 0 10 0 10 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 CCF9 CCF1 IEN9 IEN1 PTAD9 PTAD1 9 0 9 0 9 0 9 0 9 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC CCF8 CCF0 IEN8 IEN0 PTAD8 PTAD0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 0 0 CCF12 CCF4 IEN12 IEN4 PTAD12 PTAD4 12 0 12 0 12 0 12 0 12 S1C PRS3 0 0 0 0 0 CCF11 CCF3 IEN11 IEN3 PTAD11 PTAD3 11 0 11 0 11 0 11 0 11
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0080 - $00AF
Address $0099 $009A $009B $009C $009D $009E $009F $00A0 $00A1 $00A2 $00A3 $00A4 $00A5 $00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00AE $00AF Name ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L ATDDR7H ATDDR7L ATDDR8H ATDDR8L ATDDR9H ATDDR9L ATDDR10H ATDDR10L ATDDR11H ATDDR11L ATDDR12H ATDDR12L ATDDR13H ATDDR13L ATDDR14H ATDDR14L ATDDR15H ATDDR15L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD (Analog to Digital Converter 10 Bit 16 Channel)1
Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0
NOTES: 1. Registers only available on MC9S12KG128
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Device User Guide -- 9S12KT256DGV1/D V01.05
$00B0 - $00C7
Address $00B0 - $00C7 Name Reserved Read: Write:
Reserved space1
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
NOTES: 1. Reserved space for MC9S12KG128
$0080 - $009F
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 Name ATD0CTL0 ATD0CTL1 ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD0CTL5 ATD0STAT0 Reserved ATD0TEST0 ATD0TEST1 Reserved ATD0STAT1 Reserved ATD0DIEN Reserved PORTAD0 ATD0DR0H ATD0DR0L ATD0DR1H ATD0DR1L ATD0DR2H
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)1
Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: IEN7 Write: Read: 0 Write: Read: PTAD7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 0 CCF6 0 IEN6 0 PTAD6 14 Bit6 14 Bit6 14 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 0 CCF5 0 IEN5 0 PTAD5 13 0 13 0 13 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 0 0 0 CCF2 0 IEN2 0 PTAD2 10 0 10 0 10 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 0 CCF1 0 IEN1 0 PTAD1 9 0 9 0 9 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC 0 CCF0 0 IEN0 0 PTAD0 Bit8 0 Bit8 0 Bit8
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 0 0 0 CCF4 0 IEN4 0 PTAD4 12 0 12 0 12 S1C PRS3 0 0 0 0 0 0 CCF3 0 IEN3 0 PTAD3 11 0 11 0 11
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0080 - $009F
Address $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F Name ATD0DR2L ATD0DR3H ATD0DR3L ATD0DR4H ATD0DR4L ATD0DR5H ATD0DR5L ATD0DR6H ATD0DR6L ATD0DR7H ATD0DR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD0 (Analog to Digital Converter 10 Bit 8 Channel)1
Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0
NOTES: 1. Registers only available on MC9S12KT256
$00A0 - $00C7
Address $00A0 - $00C7 Name Reserved Read: Write:
Reserved space1
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
NOTES: 1. Reserved space for MC9S12KT256
$00C8 - $00CF
Address $00C8 $00C9 $00CA $00CB $00CC Name SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1
SCI0 (Asynchronous Serial Interface)
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Bit 5 0 SBR5 RSRC RIE RDRF Bit 4 SBR12 SBR4 M ILIE IDLE Bit 3 SBR11 SBR3 WAKE TE OR Bit 2 SBR10 SBR2 ILT RE NF Bit 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF
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Device User Guide -- 9S12KT256DGV1/D V01.05
$00C8 - $00CF
Address $00CD $00CE $00CF Name SCI0SR2 SCI0DRH SCI0DRL Read: Write: Read: Write: Read: Write:
SCI0 (Asynchronous Serial Interface)
Bit 7 0 R8 R7 T7 Bit 6 0 T8 R6 T6 Bit 5 0 0 R5 T5 Bit 4 0 0 R4 T4 Bit 3 0 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0
$00D0 - $00D7
Address $00D0 $00D1 $00D2 $00D3 $00D4 $00D5 $00D6 $00D7 Name SCI1BDH SCI1BDL SCI1CR1 SCI1CR2 SCI1SR1 SCI1SR2 SCI1DRH SCI1DRL
SCI1 (Asynchronous Serial Interface)
Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
$00D8 - $00DF
Address $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF Name SPI0CR1 SPI0CR2 SPI0BR SPI0SR Reserved SPI0DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI0 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$00E0 - $00E7
Address $00E0 $00E1 $00E2 $00E3 $00E4 $00E5 $00E6 $00E7 Name IBAD IBFD IBCR IBSR IBDR Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
IIC (Inter IC Bus)
Bit 7 ADR7 IBC7 IBEN TCF D7 0 0 0 Bit 6 ADR6 IBC6 IBIE IAAS D6 0 0 0 Bit 5 ADR5 IBC5 MS/SL IBB D5 0 0 0 Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 D3 0 0 0 Bit 2 ADR2 IBC2 0 RSTA SRW D2 0 0 0 Bit 1 ADR1 IBC1 0 IBIF D1 0 0 0 Bit 0 0 IBC0 IBSWAI RXAK D0 0 0 0
$00E8 - $00EF
Address $00E8 - $00EF Name Reserved Read: Write:
Reserved space
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$00F0 - $00F7
Address $00F0 $00F1 $00F2 $00F3 $00F4 $00F5 $00F6 $00F7 Name SPI1CR1 SPI1CR2 SPI1BR SPI1SR Reserved SPI1DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI1 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$00F8 - $00FF
Address $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF Name SPI2CR1 SPI2CR2 SPI2BR SPI2SR Reserved SPI2DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
SPI2 (Serial Peripheral Interface)
Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
$0100 - $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 $0108 $0109 $010A $010B $010C Name FCLKDIV FSEC FTSTMOD FCNFG FPROT FSTAT FCMD FCTL2 FADDRHI FADDRLO FDATAHI FDATALO Reserved
Flash Control Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Read: FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 Write: Read: KEYEN RNV5 RNV4 RNV3 Write: Read: 0 0 0 FDFD WRALL1 Write: Read: 0 CBEIE CCIE KEYACC DFDIE Write: Read: RNV6 FPOPEN FPHDIS FPHS Write: Read: CCIF CBEIF PVIOL ACCERR DFDIF Write: Read: 0 CMDB Write: Read: NV7 NV6 NV5 NV4 NV3 Write: Read: FADDRHI Write: Read: FADDRLO Write: Read: FDATAHI Write: Read: FDATALO Write: Read: 0 0 0 0 0 Write: Bit 2 FDIV2 RNV2 0 0 FPLDIS BLANK 0 0 0 Bit 1 FDIV1 Bit 0 FDIV0
SEC 0 BKSEL(1) FPLS 0
NV2
NV1
NV0
0
0
0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0100 - $010F
Address $010D $010E $010F Name Reserved Reserved Reserved Read: Write: Read: Write: Read: Write:
Flash Control Register
Bit 7 0 0 0 Bit 6 0 0 0 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0
NOTES: 1. Bit only available on MC9S12KT256. 2. Register only available on MC9S12KT256.
$0110 - $011B
Address $0110 $0111 $0112 $0113 $0114 $0115 $0116 $0117 $0118 $0119 $011A $011B Name ECLKDIV Reserved Reserved for Factory Test ECNFG EPROT ESTAT ECMD Reserved for Factory Test EADDRHI EADDRLO EDATAHI EDATALO
EEPROM Control Register
Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: NV6 EPOPEN Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 0 Write: Read: Bit 7 6 Write: Read: Bit 15 14 Write: Read: Bit 7 6 Write: Bit 5 EDIV5 0 0 0 NV5 PVIOL CMDB5 0 0 5 13 5 Bit 4 EDIV4 0 0 0 NV4 ACCERR 0 0 0 4 12 4 Bit 3 EDIV3 0 0 0 EPDIS 0 0 0 0 3 11 3 Bit 2 EDIV2 0 0 0 EP2 BLANK CMDB2 0 10 2 10 2 Bit 1 EDIV1 0 0 0 EP1 0 0 0 9 1 9 1 Bit 0 EDIV0 0 0 0 EP0 0 CMDB0 0 Bit 8 Bit 0 Bit 8 Bit 0
$011C - $011F
Address $011C - $011F Name Reserved Read: Write:
Reserved space
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
38
Device User Guide -- 9S12KT256DGV1/D V01.05
$0120 - $013F
Address $0120 $0121 $0122 $0123 $0124 $0125 $0126 $0127 $0128 $0129 $012A $012B $012C $012D $012E $012F $0130 $0131 $0132 $0133 $0134 $0135 $0136 $0137 $0138 Name ATD1CTL0 ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STAT0 Reserved ATD1TEST0 ATD1TEST1 Reserved ATD1STAT1 Reserved ATD1DIEN Reserved PORTAD1 ATD1DR0H ATD1DR0L ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L ATD1DR3H ATD1DR3L ATD1DR4H
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)1
Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: IEN7 Write: Read: 0 Write: Read: PTAD7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 0 CCF6 0 IEN6 0 PTAD6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 0 CCF5 0 IEN5 0 PTAD5 13 0 13 0 13 0 13 0 13 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 0 0 0 CCF2 0 IEN2 0 PTAD2 10 0 10 0 10 0 10 0 10 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 0 CCF1 0 IEN1 0 PTAD1 9 0 9 0 9 0 9 0 9 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC 0 CCF0 0 IEN0 0 PTAD0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 0 0 0 CCF4 0 IEN4 0 PTAD4 12 0 12 0 12 0 12 0 12 S1C PRS3 0 0 0 0 0 0 CCF3 0 IEN3 0 PTAD3 11 0 11 0 11 0 11 0 11
39
Device User Guide -- 9S12KT256DGV1/D V01.05
$0120 - $013F
Address $0139 $013A $013B $013C $013D $013E $013F Name ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
ATD1 (Analog to Digital Converter 10 Bit 8 Channel)1
Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0
NOTES: 1. Registers only available on MC9S12KT256. Reserved space for MC9S12KG128.
$0140 - $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D Name
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ CAN0CTL0 Write: Read: 0 SLPAK INITAK CANE CLKSRC LOOPB LISTEN WUPM CAN0CTL1 Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN0BTR0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CAN0BTR1 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF CAN0RFLG Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE CAN0RIER Write: Read: 0 0 0 0 0 TXE2 TXE1 TXE0 CAN0TFLG Write: Read: 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 CAN0TIER Write: Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 CAN0TARQ Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 CAN0TAAK Write: Read: 0 0 0 0 0 TX2 TX1 TX0 CAN0TBSEL Write: Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CAN0IDAC Write: Read: 0 0 0 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 0 0 0 Reserved Write:
40
Device User Guide -- 9S12KT256DGV1/D V01.05
$0140 - $017F
Address $014E $014F $0150 $0153 Name CAN0RXERR CAN0TXERR
CAN0 (Motorola Scalable CAN - MSCAN)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: FOREGROUND RECEIVE BUFFER see (Table 1-3) Write: Read: FOREGROUND TRANSMIT BUFFER see (Table 1-3) Write:
CAN0IDAR0 CAN0IDAR3 $0154 - CAN0IDMR0 $0157 CAN0IDMR3 CAN0IDAR4 $0158 $015B CAN0IDAR7 $015C - CAN0IDMR4 $015F CAN0IDMR7 $0160 CAN0RXFG $016F $0170 CAN0TXFG $017F
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $xxx0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 CANxRDSR0 CANxRDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CANRxDLR Write: Read: Reserved Write: Read: CANxRTSRH Write: Read: CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$xxx1
ID9
ID8
ID7
$xxx2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xxx3 $xxx4$xxxB $xxxC $xxxD $xxxE $xxxF
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15 TSR7 ID28 ID10
TSR14 TSR6 ID27 ID9
TSR13 TSR5 ID26 ID8
TSR12 TSR4 ID25 ID7
TSR11 TSR3 ID24 ID6
TSR10 TSR2 ID23 ID5
TSR9 TSR1 ID22 ID4
TSR8 TSR0 ID21 ID3
$xx10
41
Device User Guide -- 9S12KT256DGV1/D V01.05
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address $xx10 Name Extended ID CANxTIDR1 Standard ID Extended ID CANxTIDR2 Standard ID Extended ID CANxTIDR3 Standard ID CANxTDSR0 CANxTDSR7 CANxTDLR CONxTTBPR CANxTTSRH CANxTTSRL Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID20 ID2 ID14 Bit 6 ID19 ID1 ID13 Bit 5 ID18 ID0 ID12 Bit 4 SRR=1 RTR ID11 Bit 3 IDE=1 IDE=0 ID10 ID9 ID8 ID7 Bit 2 ID17 Bit 1 ID16 Bit 0 ID15
$xx12
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xx13 $xx14$xx1B $xx1C $xx1D $xx1E $xx1F
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$0180 - $01BF
Address $0180 $0181 $0182 $0183 $0184 $0185 $0186 $0187 $0188 $0189 $018A Name CAN1CTL0 CAN1CTL1 CAN1BTR0 CAN1BTR1 CAN1RFLG CAN1RIER CAN1TFLG CAN1TIER CAN1TARQ CAN1TAAK CAN1TBSEL
CAN1 (Motorola Scalable CAN - MSCAN)1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ Write: Read: 0 SLPAK INITAK CANE CLKSRC LOOPB LISTEN WUPM Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write: Read: 0 0 0 0 0 TXE2 TXE1 TXE0 Write: Read: 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 Write: Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 Write: Read: 0 0 0 0 0 TX2 TX1 TX0 Write:
42
Device User Guide -- 9S12KT256DGV1/D V01.05
$0180 - $01BF
Address $018B $018C $018D $018E $018F $0190 $0191 $0192 $0193 $0194 $0195 $0196 $0197 $0198 $0199 $019A $019B $019C $019D $019E $019F $01A0 $01AF $01B0 $01BF Name
CAN1 (Motorola Scalable CAN - MSCAN)1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CAN1IDAC Write: Read: 0 0 0 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 0 0 0 Reserved Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CAN1RXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CAN1TXERR Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR2 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR3 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR2 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR3 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR4 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR5 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR6 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR7 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR4 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR5 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR6 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR7 Write: Read: FOREGROUND RECEIVE BUFFER see (Table 1-3) CAN1RXFG Write: Read: FOREGROUND TRANSMIT BUFFER see (Table 1-3) CAN1TXFG Write:
NOTES: 1. Registers only available on MC9S12KT256. Reserved space for MC9S12KG128.
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Device User Guide -- 9S12KT256DGV1/D V01.05
$01C0 - $023F
Address $01C0 - $023F Name Reserved Read: Write:
Reserved space
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0240 - $027F
Address $0240 $0241 $0242 $0243 $0244 $0245 $0246 $0247 $0248 $0249 $024A $024B $024C $024D $024E $024F $0250 $0251 $0252 $0253 $0254 Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Integration Module)
Bit 7 PTT7 PTIT7 DDRT7 RDRT7 PERT7 PPST7 0 0 PTS7 PTIS7 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 PTM7 PTIM7 DDRM7 RDRM7 PERM7 Bit 6 PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6 0 0 PTS6 PTIS6 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 PTM6 PTIM6 DDRM7 RDRM6 PERM6 Bit 5 PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5 0 0 PTS5 PTIS5 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 PTM5 PTIM5 DDRM5 RDRM5 PERM5 Bit 4 PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4 0 0 PTS4 PTIS4 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 PTM4 PTIM4 DDRM4 RDRM4 PERM4 Bit 3 PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3 0 0 PTS3 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 RDRM3 PERM3 Bit 2 PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2 0 0 PTS2 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 RDRM2 PERM2 Bit 1 PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1 0 0 PTS1 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 RDRM1 PERM1 Bit 0 PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0 0 0 PTS0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0
44
Device User Guide -- 9S12KT256DGV1/D V01.05
$0240 - $027F
Address $0255 $0256 $0257 $0258 $0259 $025A $025B $025C $025D $025E $025F $0260 $0261 $0262 $0263 $0264 $0265 $0266 $0267 $0268 $0269 $026A $026B $026C $026D Name PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP PPSP PIEP PIFP PTH PTIH DDRH RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PIM (Port Integration Module)
Bit 7 PPSM7 Bit 6 PPSM6 Bit 5 PPSM5 Bit 4 PPSM4 Bit 3 PPSM3 Bit 2 PPSM2 Bit 1 PPSM1 Bit 0 PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 PTP7 PTIP7 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7 PTH7 PTIH7 DDRH7 RDRH7 PERH7 PPSH7 PIEH7 PIFH7 PTJ7 PTIJ7 DDRJ7 RDRJ7 PERJ7 PPSJ7 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTP6 PTIP6 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 PTH6 PTIH6 DDRH7 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 PTJ6 PTIJ6 DDRJ7 RDRJ6 PERJ6 PPSJ6 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 PTH5 PTIH5 DDRH5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 0 0 0 0 0 0 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 PTH4 PTIH4 DDRH4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 0 0 0 0 0 0 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 PTH3 PTIH3 DDRH3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 0 0 0 0 0 0 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 PTH2 PTIH2 DDRH2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 0 0 0 0 0 0 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 PTH1 PTIH1 DDRH1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1 DDRJ1 RDRJ1 PERJ1 PPSJ1 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 PTH0 PTIH0 DDRH0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0 DDRJ0 RDRJ0 PERJ0 PPSJ0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0240 - $027F
Address $026E $026F $0270 $027F Name PIEJ PIFJ Reserved Read: Write: Read: Write: Read:
PIM (Port Integration Module)
Bit 7 PIEJ7 PIFJ7 Bit 6 PIEJ6 PIFJ6 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 PIEJ1 PIFJ1 Bit 0 PIEJ0 PIFJ0
$0280 - $02BF
Address $0280 $0281 $0282 $0283 $0284 $0285 $0286 $0287 $0288 $0289 $028A $028B $028C $028D $028E $028F $0290 $0291 $0292 $0293 Name Read: CAN4CTL0 Write: Read: CAN4CTL1 Write: Read: CAN4BTR0 Write: Read: CAN4BTR1 Write: Read: CAN4RFLG Write: Read: CAN4RIER Write: Read: CAN4TFLG Write: Read: CAN4TIER Write: Read: CAN4TARQ Write: Read: CAN4TAAK Write: Read: CAN4TBSEL Write: Read: CAN4IDAC Write: Read: Reserved Write: Read: Reserved Write: Read: CAN4RXERR Write: Read: CAN4TXERR Write: Read: CAN4IDAR0 Write: Read: CAN4IDAR1 Write: Read: CAN4IDAR2 Write: Read: CAN4IDAR3 Write:
CAN4 (Motorola Scalable CAN - MSCAN)
Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 Bit 6 RXACT CLKSRC SJW0 Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH LISTEN BRP4 Bit 3 TIME 0 BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 Bit 0 INITRQ INITAK BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 CSCIF CSCIE 0 0 0 0 0 0 0 0 RSTAT1 RSTAT0 TSTAT1 TSTAT0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 0 0 0 0 0 IDAM1 0 0 0 0 0 0 0 IDAM0 0 0 0 0 0 0 0 0 0 0 TXE2 TXEIE2
ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 TX2 IDHIT2 0 0 ABTAK1 TX1 IDHIT1 0 0 ABTAK0 TX0 IDHIT0 0 0
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC7 AC7 AC7 AC6 AC6 AC6 AC6 AC5 AC5 AC5 AC5 AC4 AC4 AC4 AC4 AC3 AC3 AC3 AC3 AC2 AC2 AC2 AC2 AC1 AC1 AC1 AC1 AC0 AC0 AC0 AC0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$0280 - $02BF
Address $0294 $0295 $0296 $0297 $0298 $0299 $029A $029B $029C $029D $029E $029F $02A0 $02AF $02B0 $02BF Name CAN4IDMR0 CAN4IDMR1 CAN4IDMR2 CAN4IDMR3 CAN4IDAR4 CAN4IDAR5 CAN4IDAR6 CAN4IDAR7 CAN4IDMR4 CAN4IDMR5 CAN4IDMR6 CAN4IDMR7 CAN4RXFG CAN4TXFG Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
CAN4 (Motorola Scalable CAN - MSCAN)
Bit 7 AM7 AM7 AM7 AM7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 Bit 6 AM6 AM6 AM6 AM6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 Bit 5 AM5 AM5 AM5 AM5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 Bit 4 AM4 AM4 AM4 AM4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 Bit 3 AM3 AM3 AM3 AM3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 Bit 2 AM2 AM2 AM2 AM2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 Bit 1 AM1 AM1 AM1 AM1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 Bit 0 AM0 AM0 AM0 AM0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0
FOREGROUND RECEIVE BUFFER see (Table 1-3) FOREGROUND TRANSMIT BUFFER see (Table 1-3)
$02C0 - $02E7
Address $02C0 $02C1 $02C2 $02C3 $02C4 $02C5 $02C6 $02C7 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 7 Read: PWME7 Write: Read: PPOL7 Write: Read: PCLK7 Write: Read: 0 Write: Read: CAE7 Write: Read: CON67 Write: Read: 0 Write: Read: 0 Write: Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI 0 0 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$02C0 - $02E7
Address $02C8 $02C9 $02CA $02CB $02CC $02CD $02CE $02CF $02D0 $02D1 $02D2 $02D3 $02D4 $02D5 $02D6 $02D7 $02D8 $02D9 $02DA $02DB $02DC $02DD $02DE $02DF $02E0 Name Read: PWMSCLA Write: Read: PWMSCLB Write: Read: PWMSCNTA Write: Read: PWMSCNTB Write: Read: PWMCNT0 Write: Read: PWMCNT1 Write: Read: PWMCNT2 Write: Read: PWMCNT3 Write: Read: PWMCNT4 Write: Read: PWMCNT5 Write: Read: PWMCNT6 Write: Read: PWMCNT7 Write: Read: PWMPER0 Write: Read: PWMPER1 Write: Read: PWMPER2 Write: Read: PWMPER3 Write: Read: PWMPER4 Write: Read: PWMPER5 Write: Read: PWMPER6 Write: Read: PWMPER7 Write: Read: PWMDTY0 Write: Read: PWMDTY1 Write: Read: PWMDTY2 Write: Read: PWMDTY3 Write: Read: PWMDTY4 Write:
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 7 Bit 7 Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 Bit 2 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 Bit 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
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Device User Guide -- 9S12KT256DGV1/D V01.05
$02C0 - $02E7
Address $02E1 $02E2 $02E3 $02E4 $02E5 $02E6 $02E7 Name PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved
PWM (Pulse Width Modulator 8 Bit 8 Channel)
Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: PWMIF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 PWMIE 0 0 0 Bit 5 5 5 5 Bit 4 4 4 4 Bit 3 3 3 3 0 0 0 0 Bit 2 2 2 2 PWM7IN 0 0 0 Bit 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0
PWMRS PWMLVL TRT 0 0 0 0 0 0
PWM7IN PWM7E L NA 0 0 0 0 0 0
$02E8 - $03FF
Address $02E8 - $03FF Name Reserved Read: Write:
Reserved space
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
1.8 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset. The read-only value is a unique part ID for each revision of the chip. Table 1-4 Assigned Part ID Numbers shows the assigned part ID number. Table 1-4 Assigned Part ID Numbers
Device MC9S12KG128 MC9S12KT256 Mask Set Number 0L74N 0L33V Part ID1 $7100 $7000
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-5 shows the read-only values of these registers. Refer to HCS12 Module Mapping and Control (MMC) Block Guide for further details. Table 1-5 Memory size registers
Device MC9S12KG128 Register name MEMSIZ0 Value $13
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Device User Guide -- 9S12KT256DGV1/D V01.05
Table 1-5 Memory size registers
Device MC9S12KG128 MC9S12KT256 MC9S12KT256 Register name MEMSIZ1 MEMSIZ0 MEMSIZ1 Value $80 $25 $81
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Device User Guide -- 9S12KT256DGV1/D V01.05
Section 2 Signal Description
2.1 Device Pinout
The MC9S12K-Family and its derivatives are available in a 112-pin low profile quad flat pack (LQFP) and in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments for different packages.
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Device User Guide -- 9S12KT256DGV1/D V01.05
Figure 2-1 Pin assignments 112 LQFP for MC9S12K-Family
52
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 SS2/KWH7/PH7 SCK2/KWH6/PH6 MOSI2/KWH5/PH5 MISO2/KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ECS VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA PJ7/KWJ7/TXCAN4/SCL VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN4 PM7/TXCAN4 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
MC9S12K-Family
112LQFP
VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown in Bold are not available on the 80 Pin Package Signals shown in Italic are only available in MC9S12KT256
Device User Guide -- 9S12KT256DGV1/D V01.05
PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7SCK2 VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA PJ7/KWJ7/TXCAN4/SCL VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC9S12K-Family
80 QFP
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure 2-2 Pin assignments in 80 QFP for MC9S12K-Family
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 Signals shown in Italic are only available in MC9S12KT256
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Device User Guide -- 9S12KT256DGV1/D V01.05
2.2 Signal Properties Summary
(Table 2-1) summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package. (Table 2-2) summarizes the power and ground pins. Table 2-1 Signal Properties
Pin Name Function 1
EXTAL XTAL RESET TEST VREGEN XFC BKGD PAD[15:8]
Pin Name Function 2
-- -- -- -- -- -- TAGHI AN[15:8]
Pin Name Pin Name Powered Function 3 Function 4 by
-- -- -- -- -- -- MODC AN1[7:0]1 -- -- -- -- -- -- -- -- VDDPLL VDDPLL VDDR NA VDDX VDDPLL VDDR VDDA
Internal Pull Resistor CTRL
NA NA None NA NA NA Always Up None
Reset State
NA NA None NA NA NA Up None
Description
Oscillator Pins External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Background Debug, Tag High, Mode Input Port AD Input, Analog Inputs of ATD in MC9S12KG128, Analog Inputs of ATD1 in MC9S12KT256 Port AD Input, Analog Inputs of ATD in MC9S12KG128, Analog Inputs of ATD0 in MC9S12KT256
PAD[7:0] PA[7:0] PB[7:0] PE7 PE6
AN[7:0] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC IPIPE1
AN0[7:0]1 -- -- XCLKS MODB
-- -- -- -- --
VDDA VDDR VDDR VDDR VDDR
None PUCR PUCR PUCR
None
Disabled Port A I/O, Multiplexed Address/Data Disabled Port B I/O, Multiplexed Address/Data Up Port E I/O, Access, Clock Select Port E I/O, Pipe Status, Mode Input
While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR Up Up Up
PE5 PE4 PE3 PE2 PE1 PE0 PH7 PH6 PH5 PH4
IPIPE0 ECLK LSTRB R/W IRQ XIRQ KWH7 KWH6 KWH5 KWH4
MODA -- TAGLO -- -- -- SS2 SCK2 MOSI2 MISO2
-- -- -- -- -- -- -- -- -- --
VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR
Port E I/O, Pipe Status, Mode Input Port E I/O, Bus Clock Output Port E I/O, Byte Strobe, Tag Low Port E I/O, R/W in expanded modes Port E Input, Maskable Interrupt Port E Input, Non Maskable Interrupt
Always Up PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH
Disabled Port H I/O, Interrupt, SS of SPI2 Disabled Disabled Disabled Port H I/O, Interrupt, SCK of SPI2 Port H I/O, Interrupt, MOSI of SPI2 Port H I/O, Interrupt, MISO of SPI2
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Device User Guide -- 9S12KT256DGV1/D V01.05 Internal Pull Resistor CTRL
PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PUCR PUCR PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP
Pin Name Function 1
PH3 PH2 PH1 PH0 PJ7 PJ6 PJ[1:0] PK7 PK[5:0] PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 PP7 PP6 PP5 PP4 PP3 PP2 PP1
Pin Name Function 2
KWH3 KWH2 KWH1 KWH0 KWJ7 KWJ6 KWJ[1:0] ECS XADDR[19:14] TXCAN4 RXCAN4 TXCAN0 RXCAN0 TXCAN11 RXCAN11 TXCAN0 RXCAN0 KWP7 KWP6 KWP5 KWP4 KWP3 KWP2 KWP1
Pin Name Pin Name Powered Function 3 Function 4 by
SS1 SCK1 MOSI1 MISO1 TXCAN4 RXCAN4 -- ROMCTL -- -- -- TXCAN4 RXCAN4 TXCAN0 RXCAN0 -- -- PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 -- -- -- -- SCL SDA -- -- -- -- -- SCK0 MOSI0 SS0 MISO0 -- -- SCK2 SS2 MOSI2 MISO2 SS1 SCK1 MOSI1 VDDR VDDR VDDR VDDR VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Reset State
Disabled Disabled Disabled Disabled Up Up Up Up Up
Description
Port H I/O, Interrupt, SS of SPI1 Port H I/O, Interrupt, SCK of SPI1 Port H I/O, Interrupt, MOSI of SPI1 Port H I/O, Interrupt, MISO of SPI1 Port J I/O, Interrupt, TX of CAN4, SCL of IIC Port J I/O, Interrupt, RX of CAN4, SDA of IIC Port J I/O, Interrupts Port K I/O, Emulation Chip Select, ROM On Enable Port K I/O, Extended Addresses
Disabled Port M I/O, CAN4 TX Disabled Port M I/O, CAN4 RX Disabled Disabled Disabled Disabled Port M I/O, CAN0 TX, CAN4 TX, SPI0 SCK Port M I/O, CAN0 RX, CAN4 RX, SPI0 MOSI Port M I/O, CAN1 TX, CAN0 TX, SPI0 SS Port M I/O, CAN1 RX, CAN0 RX, SPI0 MISO
Disabled Port M I/O, CAN0 TX Disabled Port M I/O, CAN0 RX Disabled Disabled Disabled Disabled Disabled Disabled Disabled Port P I/O, Interrupt, PWM Channel 7, SCK of SPI2 Port P I/O, Interrupt, PWM Channel 6, SPI2 SS Port P I/O, Interrupt, PWM Channel 5, SPI2 MOSI Port P I/O, Interrupt, PWM Channel 4, SPI2 MISO Port P I/O, Interrupt, PWM Channel 3, SPI1 SS Port P I/O, Interrupt, PWM Channel 2, SPI1 SCK Port P I/O, Interrupt, PWM Channel 1, SPI1 MOSI
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Device User Guide -- 9S12KT256DGV1/D V01.05 Internal Pull Resistor CTRL
PERP/ PPSP PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS Up or Down
Pin Name Function 1
PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PT[7:0]
Pin Name Function 2
KWP0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0]
Pin Name Pin Name Powered Function 3 Function 4 by
PWM0 -- -- -- -- -- -- -- -- -- MISO1 -- -- -- -- -- -- -- -- -- VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Reset State
Disabled Up Up Up Up Up Up Up Up
Description
Port P I/O, Interrupt, PWM Channel 0, SPI1 MISO Port S I/O, SPI0 SS Port S I/O, SPI0 SCK Port S I/O, SPI0 MOSI Port S I/O, SPI0 MISO Port S I/O, SCI1TXD Port S I/O, SCI1RXD Port S I/O, SCI0 TXD Port S I/O, SCI0 RXD
Disabled Port T I/O, Timer channels
NOTES: 1. Only available on MC9S12KT256.
Table 2-2 Power and Ground
Mnemonic
VDD1 VDD2 VSS1 VSS2 VDDR VSSR VDDX VSSX VDDA VSSA VRH VRL VDDPLL VSSPLL
Nominal Voltage
2.5 V 0V 3.3/5.0 V 0V 3.3/5.0 V 0V 3.3/5.0 V 0V 3.3/5.0 V 0V 2.5 V 0V
Description
Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converter and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltage high for the ATD converter. Reference voltage low for the ATD converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.
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Device User Guide -- 9S12KT256DGV1/D V01.05
NOTE:
All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET -- External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
2.3.3 TEST -- Test Pin
This input only pin is reserved for test. NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN -- Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
2.3.5 XFC -- PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC R MCU CS VDDPLL VDDPLL
CP
Figure 2-3 PLL Loop Filter Connections
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Device User Guide -- 9S12KT256DGV1/D V01.05
2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET.
2.3.7 PAD[15:8] / AN[15:8] -- Port AD Input Pins [15:8]
PAD15 - PAD8 are general purpose input pins and analog inputs of the single analog to digital converter with 16 channels on MC9S12KG128. PAD15 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels (ATD1) on MC9S12KT256.
2.3.8 PAD[7:0] / AN[7:0] -- Port AD Input Pins [7:0]
PAD7 - PAD0 are general purpose input pins and analog inputs of the single analog to digital converter with 16 channels on MC9S12KG128. PAD7 - PAD0 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels (ATD0) on MC9S12KT256.
2.3.9 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
2.3.11 PE7 / NOACC / XCLKS -- Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus. The XCLKS is an input signal which controls whether a crystal in combination with the internal Loop Controlled Pierce (low power) oscillator is used or whether Full Swing Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or Full Swing Pierce Oscillator. If input is a logic high a Loop Controlled Pierce oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Loop Controlled Pierce oscillator circuit on EXTAL and XTAL.
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Table 2-3 Clock selection based on PE7 during reset
PE7
1 0
Description
Loop Controlled Pierce Oscillator selected Full Swing Pierce Oscillator or external clock selected
EXTAL
C7
MCU
XTAL
Crystal or ceramic resonator C8
VSSPLL
Figure 2-4 Loop Controlled Pierce Oscillator Connections (PE7=1)
EXTAL
C7
MCU
XTAL
RB RS*
Crystal or ceramic resonator C8
VSSPLL * Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer's data.
Figure 2-5 Full Swing Pierce Oscillator Connections (PE7=0)
EXTAL
MCU
XTAL
CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level)
not connected
Figure 2-6 External Clock Connections (PE7=0)
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2.3.12 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1.
2.3.13 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0.
2.3.14 PE4 / ECLK -- Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
2.3.15 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.16 PE2 / R/W -- Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.17 PE1 / IRQ -- Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.18 PE0 / XIRQ -- Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.19 PH7 / KWH7 / SS2 -- Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
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2.3.20 PH6 / KWH6 / SCK2 -- Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.21 PH5 / KWH5 / MOSI2 -- Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.22 PH4 / KWH4 / MISO2 -- Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.23 PH3 / KWH3 / SS1 -- Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.24 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.25 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.26 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
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2.3.27 PJ7 / KWJ7 / TXCAN4 / SCL -- PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.
2.3.28 PJ6 / KWJ6 / RXCAN4 / SDA -- PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module.
2.3.29 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
2.3.30 PK7 / ECS / ROMCTL -- Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). During MCU expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit.For all other modes the reset state of the ROMON bit is as follows: special single : ROMCTL = 1 normal single : ROMCTL = 1 emulation expanded wide : ROMCTL = 0 emulation expanded narrow : ROMCTL = 0 special test : ROMCTL = 0 peripheral test : ROMCTL = 1
2.3.31 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus.
2.3.32 PM7 / TXCAN4 -- Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 4 (CAN4).
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2.3.33 PM6 / RXCAN4 -- Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 4 (CAN4).
2.3.34 PM5 / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.35 PM4 / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).
2.3.36 PM3 / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.37 PM2 / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
2.3.38 PM1 / TXCAN0 -- Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.39 PM0 / RXCAN0 -- Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).
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2.3.40 PP7 / KWP7 / PWM7 / SCK2 -- Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.41 PP6 / KWP6 / PWM6 / SS2 -- Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.42 PP5 / KWP5 / PWM5 / MOSI2 -- Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.43 PP4 / KWP4 / PWM4 / MISO2 -- Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.44 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.45 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.46 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
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2.3.47 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.48 PS7 / SS0 -- Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.49 PS6 / SCK0 -- Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.50 PS5 / MOSI0 -- Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.51 PS4 / MISO0 -- Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.52 PS3 / TXD1 -- Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).
2.3.53 PS2 / RXD1 -- Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).
2.3.54 PS1 / TXD0 -- Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).
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2.3.55 PS0 / RXD0 -- Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).
2.3.56 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Timer (TIM).
2.4 Power Supply Pins
MC9S12K-Family power and ground pins are described below. NOTE: All VSS pins must be connected together in the application.
2.4.1 VDDX,VSSX -- Power Supply Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.2 VDDR, VSSR -- Power Supply Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 -- Power Supply Pins for Internal Logic
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE: No load allowed except for bypass capacitors.
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2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. NOTE: No load allowed except for bypass capacitors.
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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for details on clock generation.
HCS12 CORE
BDM CPU MMC DBG
Core Clock
MEBI INT
Flash RAM EEPROM EXTAL TIM ATD OSC XTAL CRG Bus Clock Oscillator Clock PWM SCI0, SCI1 SPI0, SPI1, SPI2 CAN0, CAN1, CAN4 IIC PIM
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12K-Family. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset ((Table 4-1)). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection
BKGD = MODC
0
PE6 = MODB
0
PE5 = MODA
0
PK7 = ROMCTL
X 0 1 X 0 1 X 0 1 X 0 1
ROMON Bit
1 1 0 0 1 0 1 0 1 1 0 1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
For further explanation on the modes refer to the HCS12 MEBI Block Guide.
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Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
1 0
Description
Loop Controlled Pierce Oscillator selected Full Swing Pierce Oscillator or external clock selected
Table 4-3 Voltage Regulator VREGEN
VREGEN
1 0
Description
Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * * * * Protection of the contents of FLASH, Protection of the contents of EEPROM, Operation in single-chip mode, Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block Guide for more details on the security configuration.
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4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode. Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator Guide (CRG).
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.
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4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts. Both local masking and CCR masking are included as listed in Table 5-1. System resets can be generated through external control of the RESET pin, through the clock and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
5.2.1 Vector Table
(Table 5-1) lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations
Vector Address
$FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFF0, $FFF1 $FFEE, $FFEF $FFEC, $FFED $FFEA, $FFEB $FFE8, $FFE9 $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFDC, $FFDD $FFDA, $FFDB $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3
Interrupt Source
External Reset, Power On Reset or Low Voltage Reset (see CRG Flags Register to determine reset source) Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Standard Timer channel 0 Standard Timer channel 1 Standard Timer channel 2 Standard Timer channel 3 Standard Timer channel 4 Standard Timer channel 5 Standard Timer channel 6 Standard Timer channel 7 Standard Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD0
CCR Mask
None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
Local Enable
None PLLCTL (CME, FCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSCR2 (TOI) PACTL (PAOVI) PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) SCICR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE)
HPRIO Value to Elevate
- - - - - - $F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2
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$FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD $FFCA, $FFCB $FFC8, $FFC9 $FFC6, $FFC7 $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1 $FFAE, $FFAF $FFAC, $FFAD $FFAA, $FFAB $FFA8, $FFA9 $FFA6, $FFA7 $FFA4, $FFA5 $FFA2, $FFA3 $FFA0, $FFA1 $FF9E, $FF9F $FF9C, $FF9D $FF9A, $FF9B $FF98, $FF99 $FF96, $FF97 $FF94, $FF95 $FF92, $FF93 $FF90, $FF91 $FF8E, $FF8F $FF8C, $FF8D $FF8A, $FF8B $FF80 to $FF89 CAN4 wake-up CAN4 errors CAN4 receive CAN4 transmit Port P PWM Emergency Shutdown VREG Low Voltage Interrupt Reserved ATD1 Port J Port H Reserved CRG PLL lock CRG Self Clock Mode FLASH Double Fault Detect IIC Bus SPI1 SPI2 EEPROM command FLASH command CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit CAN1 wake-up CAN1 errors CAN1 receive CAN1 transmit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved CAN4RIER (WUPIE) CAN4RIER (CSCIE, OVRIE) CAN4RIER (RXFIE) CAN4TIER (TXEIE2 - TXEIE0) PIEP (PIEP7-0) PWMSDN (PWMIE) CTRL0 (LVIE) Reserved ATDCTL2 (ASCIE)1 PIEJ (PIEJ7, PIEJ6, PIEJ1, PIEJ0) PIEH (PIEH7-0) Reserved CRGINT (LOCKIE) CRGINT (SCMIE) FCNFG (DFDIE) IBCR (IBIE) SPICR1 (SPIE, SPTIE) SPICR1 (SPIE, SPTIE) ECNFG (CCIE, CBEIE) FCNFG (CCIE, CBEIE) CAN0RIER (WUPIE) CAN0RIER (CSCIE, OVRIE) CAN0RIER (RXFIE) CAN0TIER (TXEIE2 - TXEIE0) CAN1RIER (WUPIE)1 CAN1RIER (CSCIE, OVRIE)1 CAN1RIER (RXFIE)1 CAN1TIER (TXEIE2 TXEIE0)1 $D0 $CE $CC $CA $C8 $C6 $C4 $C2 $C0 $BE $BC $BA $B8 $B6 $B4 $B2 $B0 $AE $AC $AA $A8 $A6 $A4 $A2 $A0 $9E $9C $9A $98 $96 $94 $92 $90 $8E $8C $8A
NOTES: 1. Interrupt vector is only available on MC9S12KT256. Otherwise it is reserved.
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5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a system reset are summarized in Table 5-2. Table 5-2 Reset Summary
Reset
Power-on Reset External Reset Low Voltage Reset Clock Monitor Reset COP Watchdog Reset
Priority
1 1 1 2 3
Source
CRG Module RESET pin VREG Module CRG Module CRG Module
Vector
$FFFE, $FFFF $FFFE, $FFFF $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode dependent pin configuration of port A, B and E out of reset. Refer to the PIM Block Guide for reset configurations of all peripheral module ports. Refer to Table 1-1(Table 1-1) for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit. When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods. So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Background Debug Module (BDM) Block Description
Consult the HCS12 BDM Block Guide for information about the Background Debug Module. When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
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6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface module.
6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module for the MC9S12KG128. When the ATD_10B16C Block Guide refers to freeze mode this is equivalent to active BDM mode. Consult the ATD_10B8C Block Guide for further information about the A/D Converter module for the MC9S12KT256. When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 8 Clock Reset Generator (CRG) Block Description
8.1
Consult the CRG Block Guide for information about the Clock and Reset Generator module.Device-specific
information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the VREG Block Guide for voltage level specifications.
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Section 9 EEPROM Block Description
Consult the EETS2K Block Guide for information about the EEPROM module for the MC9S12KG128. Consult the EETS4K Block Guide for information about the EEPROM module for the MC9S12KT256.
Section 10 Flash EEPROM Block Description
Consult the FTS128K1ECC Block Guide for information about the flash module for the MC9S12KG128. Consult the FTS256K2ECC Block Guide for information about the flash module for the MC9S12KT256. The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its implementation, please see the S12 LREA Application Note (AN2546/D) . It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE programmed in the Flash . Exact details of the changeover (ie blank to programmed) for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device. Please contact Motorola SPS Sales if you have any additional questions.
Section 11 IIC Block Description
Consult the IIC Block Guide for information about the Inter-IC Bus module.
Section 12 MSCAN Block Description
There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12KT256. There are only two MSCAN modules (CAN4 and CAN0) implemented on the MC9S12KG128. Consult the MSCAN Block Guide for information about the Motorola Scalable CAN Module.
Section 13 OSC Block Description
Consult the OSC_LCP Block Guide for information about the Oscillator module.
Section 14 Port Integration Module (PIM) Block Description
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Consult the PIM_9KG128 Block Guide for information about the Port Integration Module for the MC9S12KG128. Consult the PIM_9KT256 Block Guide for information about the Port Integration Module for the MC9S12KT256.
Section 15 Pulse Width Modulator (PWM) Block Description
Consult the PWM_8B8C Block Guide for information about the Pulse Width Modulator Module. When the PWM_8B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 16 Serial Communications Interface (SCI) Block Description
There are two Serial Communications Interface modules (SCI1 and SCI0). Consult the SCI Block Guide for information about the Serial Communications Interface module.
Section 17 Serial Peripheral Interface (SPI) Block Description
There are three Serial Peripheral Interfaces (SPI2, SPI1 and SPI0) implemented on MC9S12K-Family. Consult the SPI Block Guide for information about each Serial Peripheral Interface module.
Section 18 Timer (TIM) Block Description
Consult the TIM_16B8C Block Guide for information about the Timer module. When the TIM_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 19 Voltage Regulator (VREG) Block Description
Consult the VREG_3V3 Block Guide for information about the dual output linear voltage regulator.
19.1 Device-specific information
19.1.1 VDD1, VDD2, VSS1, VSS2
In both the 112 pin LQFP and the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1
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and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally. This allows systems to employ better supply routing and further decoupling.
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Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice.
This supplement contains the most accurate electrical information for the MC9S12K-Family of microcontrollers available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE: P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. They are regularly verified by production monitors. T: Those parameters are achieved by design characterization on a small sample size from typical devices. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations. This classification is shown in the column labeled "C" in the parameter tables where appropriate.
A.1.2 Power Supply
The MC9S12K-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter. The VDDX, VSSX pair supplies the I/O pins
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The VDDR, VSSR pair supplies the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic. VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 3.3V/5V I/O pins Those I/O pins have a nominal level of 3.3V or 5V depending on the application operating point. This group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group of pins is comprised of the VRH and VRL pins. A.1.3.3 Oscillator The pins EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 PLL The pin XFC dedicated to the oscillator have a nominal 2.5V level. It is supplied by VDDPLL. A.1.3.5 TEST This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation.
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Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage1 PLL Supply Voltage (1) Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 2 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL3 Instantaneous Maximum Current Single pin limit for TEST4 Operating Temperature Range (packaged) Operating Temperature Range (junction) Storage Temperature Range
Symbol
VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST I
D
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 - 40 - 40 - 65
Max
6.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 10.0 +25 +25 0 125 140 155
Unit
V V V V V V V V V mA mA mA C C C
IDL I
DT A
T
TJ T
stg
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 3. These pins are internally clamped to VSSPLL and VDDPLL 4. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Maximum input voltage limit
Description
Symbol
R1 C R1 C -
Value
1500 100 3 3 0 200 3 3 -2.5 7.5
Unit
Ohm pF
Ohm pF
Latch-up
V V
Table A-3 ESD and Latch-Up Protection Characteristics
Num
1 2 3 4
C
C C C C
Rating
Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current at 125C positive negative Latch-up Current at 27C positive negative
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-
Unit
V V V mA
5
C
ILAT
-
mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
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NOTE:
Instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating Symbol
VDD5 VDD VDDPLL VDDX VSSX fosc fbus
Min
3.15 2.35 2.35 -0.1 -0.1 0.5 0.5
Typ
3.3/5 2.5 2.5 0 0 -
Max
5.5 2.75 2.75 0.1 0.1 16 25
Unit
V V V V V MHz MHz
I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage1 PLL Supply Voltage (1) Voltage Difference VDDX to VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC9S12KG128C/MC9S12KT256C Operating Junction Temperature Range Operating Ambient Temperature Range 2 MC9S12KG128V/MC9S12KT256V Operating Junction Temperature Range Operating Ambient Temperature Range (2) MC9S12KG128M/MC9S12KT256M Operating Junction Temperature Range Operating Ambient Temperature Range (2)
TJ T
A
-40 -40
27
100 85
C C
TJ TA
-40 -40
27
120 105
C C
TJ TA
-40 -40
27
140 125
C C
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ]
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P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD V DD + I DDPLL V DDPLL + I DDA V DDA 2 P IO = R DSON I IO i i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL
V DD5 - V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i
respectively
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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Table A-5 Thermal Package Characteristics1
Num
1 2 3 4
C
Rating
Symbol
JA JA JA JA
Min
-
Typ
-
Max
54 41 51 41
Unit
oC/W
oC/W
T Thermal Resistance LQFP112, single sided PCB2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3
T Thermal Resistance QFP 80, single sided PCB T Thermal Resistance QFP 80, double sided PCB with 2 internal planes
oC/W
o
C/W
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3
C
P P Input High Voltage Input Low Voltage
Rating
Symbol
V
IH
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5
Unit
V V mV A
VIL VHYS I
C Input Hysteresis Input Leakage Current (pins in high ohmic input mode)1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) Partial Drive IOH = -2.0mA Full Drive IOH = -10.0mA Output Low Voltage (pins in output mode) Partial Drive IOL = +2.0mA Full Drive IOL = +10.0mA Internal Pull Up Device Current, tested at V Max.
IL
4
P
in
-2.5
-
2.5
5
P
V
OH
VDD5 - 0.8
-
-
V
6
P
VOL
-
-
0.8
V
7 8 9 10 11 12 13 14
P P P P
IPUL IPUH IPDH IPDL Cin IICS IICP tpign tpval
-10 10
6
-130 130 2.5 25 3
A A A A pF mA s s
Internal Pull Up Device Current, tested at VIH Min. Internal Pull Down Device Current, tested at V Min.
IH
Internal Pull Down Device Current, tested at VIL Max.
D Input Capacitance T P P Injection current2 Single Pin limit Total Device Limit. Sum of all injected currents Port H, J, P Interrupt Input Pulse filtered3 Port H, J, P Interrupt Input Pulse passed(3)
-2.5 -25
-
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 Preliminary 3.3V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 P Input High Voltage P Input Low Voltage C Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD5 VSS5 - 0.3
Typ
250
Max
VDD5 + 0.3 0.35*VDD5
Unit
V V mV A
VIL VHYS I
4
Input Leakage Current (pins in high ohmic input P mode)1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) P Partial Drive IOH = -2.0mA Full Drive IOH = -10.0mA Output Low Voltage (pins in output mode) P Partial Drive IOL = +2.0mA Full Drive IOL = +10.0mA Internal Pull Up Device Current, P tested at V Max.
IL
in
-2.5
-
2.5
5
V
OH
VDD5 - 0.8
-
-
V
6
VOL
-
-
0.8
V
7 8 9 10 11 12 13 14
IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE tPULSE
-10 10
6
-130 130 2.5 25 3
A A A A pF mA s s
Internal Pull Up Device Current, P tested at V Min. IH Internal Pull Down Device Current, P tested at V Min.
IH
Internal Pull Down Device Current, P tested at V Max. IL D Input Capacitance Injection current2 T Single Pin limit Total Device Limit. Sum of all injected currents P Port P, J Interrupt Input Pulse filtered3 P Port P, J Interrupt Input Pulse passed(3)
-2.5 -25
-
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements.
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A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.
Table A-8 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1
Rating
Run supply currents Single Chip, Internal regulator enabled Wait Supply current All modules enabled only RTI enabled Pseudo Stop Current (RTI and COP enabled) -40C 27C 70C 85C 105C 125C 135xC Pseudo Stop Current (RTI and COP disabled) -40C 27C 70C 85C 105C 125C 135C Stop Current -40C 27C 70C 85C 105C 125C 135C
Symbol
IDD5 IDDW
Min
Typ
Max
65 40 5
Unit
mA
2
mA
3
IDDPS
TBD 600 TBD TBD TBD TBD 1000 TBD 160 TBD TBD TBD TBD 700 TBD 30 TBD 200 TBD TBD 500
750 A
5000
400 A
4
IDDPS
5000
100 A
5
IDDS
5000
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A.2 Voltage Regulator (VREG_3V3) Operating Characteristics
This section describes the characteristics of the on chip voltage regulator. Table 19-1 VREG_3V3 - Operating Conditions
Num
1 2
C
P P
Characteristic
Input Voltages Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Reduced Power Mode Shutdown Mode1 Output Voltage PLL Full Performance Mode Reduced Power Mode2 Shutdown Mode(1) Low Voltage Interrupt3 Assert Level Deassert Level Low Voltage Reset4 Assert Level Deassert Level Power-on Reset5 Assert Level Deassert Level
Symbol
VVDDR,A IREG
Min
3.135 -- -- 2.35 1.6 --
Typical
-- 20 12 2.5 2.5 -- 2.5 2.5 --
Max
5.5 50 40 2.75 2.75 --
Unit
V A A V V V
3
P
VDD
4
P
VDDPLL
2.35 1.6 --
2.75 2.75 --
V V V
5
P
VLVIA VLVID VLVRA VLVRD VPORA VPORD
4.1 4.25
4.37 4.52
4.66 4.77 -- 2.55
V V
5
P
2.25 --
-- --
V V
7
C
0.97 --
-----
-- 2.05
V V
NOTES: 1. High Impedance Output 2. Current IDDPLL = 3mA 3. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 4. Monitors VDD, active only in Full Performance Mode. VLVRA and VPORD must overlap 5. Monitors VDD. Active in all modes.
NOTE:
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Motorola and are subject to change without notice.
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A.3 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-1. Figure A-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) V
VLVID VLVIA VDD VDDA
VLVRD VLVRA VPORD
t
LVI
POR
LVI enabled
LVI disabled due to LVR
LVR
A.4 Output Loads
A.4.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads.
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A.4.2 Capacitive Loads
The capacitive loads are specified in Table A-9. Ceramic capacitors with X7R dielectricum are required. Table A-9 Voltage Regulator - Capacitive Loads
Num
1 2
Characteristic
VDD external capacitive load VDDPLL external capacitive load
Symbol
CDDext CDDPLLext
Min
200 90
Typical
440 220
Max
12000 5000
Unit
nF nF
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A.5 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.5.1 ATD Operating Characteristics
The Table A-10 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-10 5V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Reference Potential 1 2 3 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 TCONV10 NCONV8 TCONV8 tSR IREF IREF
Min VSSA VDDA/2 4.75 0.5 14 7 3.5 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s s Cycles s s mA mA
C Differential Reference Voltage1 D ATD Clock Frequency ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK Conv, Time at 4.0MHz3 ATD Clock fATDCLK ATD 8-Bit Conversion Period
5.0
5.25 2.0 28 14 7 26 13 20 0.750 0.375
4
D
5 6 7 8
D
Clock Cycles(1) Conv, Time at 2.0MHz ATD Clock fATDCLK
D Stop Recovery Time (VDDA=5.0 Volts) P Reference Supply current (two ATD modules) P Reference Supply current (one ATD module)
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.75V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. 3. Reduced accuracy see Table A-13 and Table A-14.
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Table A-11 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%
Num C
Reference Potential 1 2 3 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 3.0 0.5 14 7 3.5 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s s Cycles s s mA mA
C Differential Reference Voltage D ATD Clock Frequency ATD 10-Bit Conversion Period
3.3
3.6 2.0 28 14 7 26 13 20 0.500 0.250
4
D
Clock Cycles1 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK T Conv, Time at 4.0MHz2 ATD Clock fATDCLK ATD 8-Bit Conversion Period
TCONV10 NCONV8 TCONV8 tREC IREF IREF
CONV10
5 6 7 8
D
Clock Cycles(1) Conv, Time at 2.0MHz ATD Clock fATDCLK
D Recovery Time (VDDA=3.3 Volts) P P Reference Supply current (two ATD modules) Reference Supply current (one ATD module)
NOTES: 1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. 2. Reduced accuracy see Table A-13 and Table A-14.
A.5.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. A.5.2.1 Source Resistance: Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance are allowed. A.5.2.2 Source capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). A.5.2.3 Current injection There are two cases to consider.
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1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-12 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5
Rating
Max input Source Resistance Total Input Capacitance Non Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
Symbol
RS CINN CINS INA Kp Kn
Min
-
Typ
-
Max
1 10 22
Unit
K pF mA A/A A/A
-2.5
2.5 10-4 10-2
A.5.3 ATD accuracy
Table A-13 and Table A-14 specify the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-13 5V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz Num
1 2 3 4 5 6 7 8 9
C
P 10-Bit Resolution
Rating
Symbol
LSB DNL INL AE AE LSB DNL INL AE
Min
-1 -2.5 -3
Typ
5
Max
1
Unit
mV Counts Counts Counts Counts mV
P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 C 10-Bit Absolute Error at fATDCLK= 4MHz P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error(1)
1.5 2.0 7.0 20
2.5 3
-0.5 -1.0 -1.5 0.5 1.0
0.5 1.0 1.5
Counts Counts Counts
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NOTES: 1. These values include quantization error which is inherently 1/2 count for any A/D converter.
Table A-14 3.3V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz Num C
1 2 3 4 5 6 7 8 9 P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 C 10-Bit Absolute Error at fATDCLK= 4MHz P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error(1)
Rating
Symbol
LSB DNL INL AE AE LSB DNL INL AE
Min
-1.5 -3.5 -5
Typ
3.25
Max
1.5
Unit
mV Counts Counts Counts Counts mV
1.5 2.5 7.0 13
3.5 5
-0.5 -1.5 -2.0 0.1 1.5
0.5 1.5 2.0
Counts Counts Counts
NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-2. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ----------------------- - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n Vn - V0
INL ( n ) =
DNL ( i ) =
------------------- - n 1LSB
i=1
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DNL 10-Bit Absolute Error Boundary
LSB Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
Vi
8-Bit Absolute Error Boundary
$FF
$FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure A-2 ATD Accuracy Definitions NOTE:Figure A-2 shows only definitions, for specification values refer to Table A-13 and Table A-14 .
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A.6 NVM, Flash and EEPROM
NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM.
A.6.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-15 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.6.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9 --------------------- + 25 --------f bus f NVMOP
A.6.1.2 Row Programming Flash programming where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4 --------------------- + 9 --------f bus f NVMOP
The time to program a whole row is:
t brpgm = t swpgm + 31 t bwpgm
Row programming is more than 2 times faster than single word programming. A.6.1.3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
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The setup time can be ignored for this operation. A.6.1.4 Mass Erase Erasing a NVM block takes:
1 t era 4000 --------------------f NVMOP
The setup time can be ignored for this operation. A.6.1.5 Blank Check
1 t mass 20000 --------------------f NVMOP
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command.
t check location t cyc + 10 t cyc
Table A-15 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10
Rating
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck
Min
0.5 1 150 46 2 20.4 (2) 678.4 (2) 20 5 100 (5) 11 6 11 (6)
Typ
Max
50 1
Unit
MHz MHz
D External Oscillator Clock D Bus frequency for Programming or Erase Operations D Operating Frequency P Single Word Programming Time D Flash Burst Programming consecutive word 4 D Flash Burst Programming Time for 32 Words (4) P Sector Erase Time P Mass Erase Time D Blank Check Time Flash per block D Blank Check Time EEPROM per block
200 74.5 3 31 (3) 1035.5 (3) 26.7 (3) 133 (3) 32778 7 2058(7)
kHz s s s ms ms tcyc tcyc
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.6.1.1 Single Word Programming- Section A.6.1.4 Mass Erasefor guidance. 4. urst Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block
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A.6.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE: All values shown in Table A-16 are target values and subject to further extensive characterization. Table A-16 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 C
Rating
Data Retention at an average junction temperature of TJavg = 70C
Symbol
tNVMRET nFLPE nEEPE nEEPE
Min
15 1000 10,000 100,000
Typ
Max
Unit
Years
C Flash number of Program/Erase cycles C C EEPROM number of Program/Erase cycles (-40C TJ 0C) EEPROM number of Program/Erase cycles (0C < TJ 140C)
10,000
Cycles Cycles Cycles
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A.7 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
A.7.1 Startup
Table A-17 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-17 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 T POR release level T POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS
Min
Typ
Max
2.07
Unit
V V tosc
0.97 2 192 20 14 196
D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time
nosc ns tcyc
A.7.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.7.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.7.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. A.7.1.4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system.
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A.7.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
A.7.2 Oscillator
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Full swing Pierce oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA Table A-18 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1a 1b 2 3 4 5 6 7 8 9 10 11 12
Rating
Symbol
fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VIH,EXTAL VIH,EXTAL VIL,EXTAL VIL,EXTAL VHYS,EXTA
L
Min
4.0 0.5 100
Typ
Max
16 40
Unit
MHz MHz A
C Crystal oscillator range (loop controlled Pierce) C Crystal oscillator range (full swing Pierce) 1,2 P Startup Current C Oscillator start-up time (loop controlled Pierce) D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency 2 D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance (EXTAL, XTAL pins) P EXTAL Pin Input High Voltage T EXTAL Pin Input High Voltage
TBD3 0.45 50 0.5 9.5 9.5 100
504 2.5 200 50
ms s KHz MHz ns ns
1 1 7 0.7*VDDPLL VDDPLL + 0.3 0.3*VDDPLL VSSPLL - 0.3 250
ns ns pF V V V V mV
13
P EXTAL Pin Input Low Voltage T EXTAL Pin Input Low Voltage
14
C EXTAL Pin Input Hysteresis
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NOTES: 1. Depending on the crystal a damping series resistor might be necessary 2. Only valid if full swing Pierce oscillator/external clock mode is selected 3. fOSC = 4MHz, C = 22pF. 4. Maximum value is for extreme cases using high Q, low frequency crystals
A.7.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.7.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp VDDPLL Cs fosc fref 1 refdv+1 fcmp R Phase K Detector Loop Divider 1 synr+1
XFC Pin
VCO KV fvco
1 2
Figure A-3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-19. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: ( f 1 - f vco ) ---------------------K 1 1V ( 60 - 50 ) ----------------------- 100
KV = K1 e
= - 100 e
= -90.48MHz/V
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The phase detector relationship is given by:
K = - i ch K V
ich is the current in tracking mode.
= 316.7Hz/
The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ----- f C < ------------- ;( = 0.9 ) 10 4 10 2 + 1 + fC < 25kHz
And finally the frequency relationship is defined as
f VCO n = ------------ = 2 ( synr + 1 ) f ref
= 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz:
2 n fC R = ---------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k=~10k K
The capacitance Cs can now be calculated as:
2 - 0.516 C s = --------------------- -------------- ;( = 0.9 ) = 5.19nF =~ 4.7nF fC R fC R
The capacitance Cp should be chosen in the range of:
2
C s 20 C p C s 10
A.7.3.2 Jitter Information NOTE: This section is under construction
Cp = 470pF
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
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Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN
Figure A-4 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t min ( N ) t max ( N ) J ( N ) = max 1 - -------------------- , 1 - -------------------- N t nom N t nom
NOTE: From the evaluation data a formula for tmax= f(N), resp. tmin = f(N) should be derived.
Assuming no long term drift of the reference clock, the following will hold N
lim J ( N ) = 0
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
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Table A-19 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
Symbol
fSCM fVCO trk Lock unl unt tstab tacq tal K1 f1 ich ich j1 j2
Min
1 8 3% 0% 0.5% 6%
Typ
Max
5.5 50 4%1 1.5%(1) 2.5%(1) 8%(1)
Unit
MHz MHz -- -- -- -- ms ms ms MHz/V MHz A A
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode
D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode
C PLLON Total Stabilization delay2 D PLLON Acquisition mode stabilization delay(2) D PLLON Tracking mode stabilization delay(2) D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter fit parameter 1(2) C Jitter fit parameter 2(2)
0.5 0.3 0.2 -100 60 -38.5 -3.5 1.1 0.13
% %
NOTES: 1. % deviation from target frequency 2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K.
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A.8 MSCAN
Table A-20 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2
Rating
Symbol
tWUP tWUP
Min
Typ
Max
2
Unit
s s
P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass
5
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A.9 SPI
A.9.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-21.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT)
1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
11
3
12
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 10
Figure A-5 SPI Master Timing (CPHA = 0)
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SS1 (OUTPUT) 1 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
2
12
11
3
4
4
11
12
5
6 MSB IN2 BIT 6 . . . 1 10 LSB IN
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure A-6 SPI Master Timing (CPHA =1) Table A-21 SPI Master Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num
1 1 2 3 4 5 6 9 10 11 12
C
P P D D D D D D D D D
Rating
Operating Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid (after SCK Edge) Data Hold Time (Outputs) Rise Time Inputs and Outputs Fall Time Inputs and Outputs
Symbol
fop tsck tlead tlag twsck tsu thi tv tho tr tf
Min
DC 4 1/2 1/2 tbus - 30 25 0
Typ
Max
1/4 2048 --
Unit
fbus tbus tsck tsck
1024 tbus
ns ns ns
25 0 25 25
ns ns ns ns
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A.9.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-22.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) 2 4 4 11 12 8 7 MISO (OUTPUT) SLAVE MSB OUT 5 MOSI (INPUT) 6 MSB IN BIT 6 . . . 1 LSB IN 9 BIT 6 . . . 1 10 10 SEE NOTE 12 11 3
SLAVE LSB OUT
NOTE: Not defined but normally MSB of character just received.
Figure A-7 SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) MOSI (INPUT) SEE NOTE 7 2 12 11 3
4
4
11
12
9 SLAVE MSB OUT 5 6 MSB IN
10 BIT 6 . . . 1 SLAVE LSB OUT
8
BIT 6 . . . 1
LSB IN
NOTE: Not defined but normally LSB of character just received.
Figure A-8 SPI Slave Timing (CPHA =1)
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Table A-22 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num
1 1 2 3 4 5 6 7 8 9 10 11 12
C
Rating
Symbol
fop tsck tlead tlag twsck tsu thi ta tdis tv tho tr tf
Min
DC 4 1 1 tcyc - 30 25 25
Typ
Max
1/4 2048
Unit
fbus tbus tcyc tcyc ns ns ns
P Operating Frequency P SCK Period D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Slave Access Time D Slave MISO Disable Time D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
1 1 25 0 25 25
tcyc tcyc ns ns ns ns
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A.10 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-23. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.10.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
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1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 16 10 data 11 4
17 Non-Multiplexed Addresses PK5:0 20 ECS PK7 24 R/W PE2
18
19
21
22
23
25
26
27 LSTRB PE3
28
29
30 NOACC PE7 33 PIPO0 PIPO1, PE6,5
31
32
34
35
36
Figure A-9 General External Bus Timing
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Table A-23 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
C
Rating
Symbol
fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV
Min
0 40 17 17
Typ
Max
25.0
Unit
1 2 3 4
P Frequency of operation (E-clock) P Cycle time D Pulse width, E low D Pulse width, E high1 D Address delay time D Address valid time to E rise (PWEL-tAD) D Muxed address hold time D Address hold to data valid D Data hold to address D Read data setup time D Read data hold time D Write data delay time D Write data hold time D Write data setup time(1) (PWEH-tDDW) D Address access time(1) (tcyc-tAD-tDSR) D E high access time(1) (PWEH-tDSR) D Non-multiplexed address delay time D Non-muxed address valid to E rise (PWEL-tNAD) D Non-multiplexed address hold time D Chip select delay time D Chip select access time(1) (tcyc-tCSD-tDSR) D Chip select hold time D Chip select negated time D Read/write delay time D Read/write valid time to E rise (PWEL-tRWD) D Read/write hold time D Low strobe delay time D Low strobe valid time to E rise (PWEL-tLSD) D Low strobe hold time D NOACC strobe delay time D NOACC valid time to E rise (PWEL-tLSD)
8 11 2 7 2 13 0 7 2 10 19 4 7 10 2 16 11 2 8 7 10 2 7 10 2 7 10
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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Table A-23 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF 32 33 34 35 36 D NOACC hold time D PIPO0 delay time D PIPO0 valid time to E rise (PWEL-tP0D) D PIPO1 delay time(1) (PWEH-tP1V) D PIPO1 valid time to E fall tNOH tP0D tP0V tP1D tP1V 2 2 10 2 10 7 7 32 33 34 35 36
NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12-Family packages.
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B.2 80-pin QFP package
L
60 61 41 40
S
S
B B P
D
L
0.20 M H A-B
B
V 0.05 D
0.20 M C A-B
-A-
-B-
S
S
D
-A-,-B-,-DDETAIL A
DETAIL A
80 1
21
-DA 0.20 M H A-B 0.05 A-B S 0.20 M C A-B
S S
20
F
D
S
J D
S
N
E C -CSEATING PLANE
M
D DETAIL C -HDATUM PLANE
0.20 M C A-B SECTION B-B
S
D
S
VIEW ROTATED 90
H G
0.10 M
U T
DATUM -HPLANE
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure B-1 80-pin QFP Mechanical Dimensions (case no. 841B)
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B.3 112-pin LQFP package
4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M V
B1
V1
J
AA
28 29 56
57
F D 0.13
M
BASE METAL
N A1 S1 A S
T L-M N
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --- 1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 R1 0.25
GAGE PLANE
R
C1 (Y) VIEW AB (Z)
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure B-2 112-pin LQFP Mechanical Dimensions (case no. 987)
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Device User Guide End Sheet
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FINAL PAGE OF 126 PAGES
126

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